This invention relates to a method and apparatus for evaluating surface features such as those on a partially fabricated integrated circuit. More specifically, the invention relates to methods and apparatus for using the far-field pattern of scattered and diffracted light from the surface features to evaluate the quality or condition of the features.
Many optical and electronic systems exist for identifying and classifying surface feature errors such as those on a partially fabricated integrated circuit or a reticle. These errors may take the form of particles randomly localized on the surface, scratches, process variations such as under etching, etc. Such techniques and apparatus are well known in the art and are embodied in various commercial products such as many of those available from KLA-Tencor Corporation of San Jose, Calif.
Relatively few techniques are available for evaluating the condition of surface features (e.g., contacts, vias, deep trenches, polysilicon gate structures, reticle features, etc.). Most generally, these surface features may be viewed as design features which show up as topological variations on a surface. Often, one wishes to know whether or not such features (as formed in a conventional process) fall within specified tolerances. For example, the depth, diameter and slope of a contact hole or via should fall within specified tolerances. If a contact hole is etched too deeply, it may cut into the substrate and thereby detrimentally effect the electrical performance of a transistor. An over etched via may cut through an underlying contact to change resistance, etc. If a via is under etched (not sufficiently deep), there may be no contact between an upper level metallization line and a lower level metallization. If a via is etched too narrowly, the current density in the resulting interconnect may be too high, possibly resulting in premature failure.
These and similar problems often arise when processing equipment malfunctions or degrades in performance over time. Examples of such equipment include plasma etchers, deposition systems, chemical mechanical planarization systems, reticle processing, and photolithography equipment. Obviously, a manufacturer needs to know when the process equipment ceases to function in an acceptable manner.
A few techniques do exist for evaluating the condition of topologic features on a reticle or integrated circuit. The simplest of these involves a casual visual inspection by a technician of a wafer held in white light and examined to determine whether there is any variation in the appearance of the various dies fabricated on the wafer. Ideally, each die should have the same appearance when moved about under a white light. If there is any variation in the appearance of one or more of the dies on the wafer, then it can be assumed the dies are not structurally identical and some problem exists. A related technique simply involves performing optical microscopy (e.g., bright field or dark field imaging) on the various dies of a wafer. Any variation in the image of the individual die indicates that there is a problem in at least that die. However, due to the trend of small design rule, high aspect ratio, and the complexity of the background circuit, defective vias or contact holes are at times difficult to detect through standard microscopic methods.
More accurate techniques exist for evaluating surface features. For example, ion milling may be employed to evaluate the condition of a section of an integrated circuit. Ion milling cuts through the circuit creating a cross section at a location of interest, possibly an area where vias are suspected of being defective. Subsequently, a scanning electron micrograph images the cross section. From this, over etching, under etching, defective profiles, etc. in the vias can be visualized. Unfortunately, this technique destroys the integrated circuit.
In some cases, scanning electron microscopy or a similar electron beam technique is employed to image the surface of a die (as opposed to a cross section). While this technique does not necessarily destroy the integrated circuit, the electrons may damage the substrate surface. Further, both ion milling and scanning electron microscopy are currently very slow processes and therefore unsuitable for regular use in the normal process flow of an integrated circuit fabrication facility.
What is needed therefore is a rapid, non-destructive, and inexpensive technique for evaluating non-random topological variations on the surface of a substrate such as a partially fabricated integrated circuit or a reticle.